1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more particularly to, a method for manufacturing a flash memory device which can minimize a hole current by impurity diffusion of floating gates, obtain a sufficient capacitance for a cell operation by increasing a breakdown voltage, and improve retention properties of a flash memory cell, by filing up an impurity on an oxide film and a polysilicon film, by forming the oxide film on the polysilicon film used as the floating gates, doping an impurity into the oxide film, and annealing the oxide film.
2. Discussion of Related Art
A flash memory device uses a polysilicon film doped with an impurity such as P as floating gates. A cleaning process using HF or a buffered oxide etch (BOE) solution is performed after forming the polysilicon film and before forming a dielectric film. Here, P doped into the polysilicon film is removed. When a cleaning process using a standard clean #1 (SC-1) solution is performed, a natural oxide film is grown on the polysilicon film. The natural oxide film rarely contains P. Therefore, P of the polysilicon film is diffused into the natural oxide film in a succeeding annealing process. On the other hand, when the polysilicon film is doped with P after the cleaning process using HF, a buffer layer for preventing diffusion of P is not formed, and thus P is diffused in a succeeding annealing process.
In the case that the flash memory device is manufactured according to a general method, a margin of a breakdown voltage is deficient, and thus a thickness of the dielectric film is not reduced. In addition, when the floating gates are formed into a merged PIN/Schottky structure (MPS) to improve a capacitance and a surface area of the MPS is increased, the breakdown voltage sharply decreases. After an etching process for forming a gate, the sides of the gate are oxidized at a predetermined thickness to buffer a stress caused by the etching process. However, an oxide film is grown on the interface between the polysilicon film and a lower oxide film of the dielectric film due to the oxidation process, and thus an effective oxide film thickness Teff of the dielectric film is different at the inside and outside of the gate. That is, the effective oxide film thickness Teff is not uniform. Moreover, the dielectric film is thickened to increase the effective oxide film thickness Teff and reduce the capacitance. Such irregular oxidation causes leakage and reduces the breakdown voltage, which has the detrimental effects on the cell operation.